The present invention relates generally to semiconductor devices, and more particularly to a voltage regulator with a distributed output transistor.
Semiconductor devices are used for integrated circuits in a variety of electrical and electronic applications, such as computers, cellular telephones, radios, and televisions, as examples. One particular type of semiconductor device is a semiconductor storage device, such as a random access memory (RAM) device. RAM devices use an electrical charge to store information. RAM devices include many storage cells arranged in a two-dimensional array with two sets of select lines, referred to as wordlines and bitlines. An individual storage cell is selected by activating its wordline and its bitline. RAM devices are considered xe2x80x9crandom accessxe2x80x9d because any memory cell in an array can be accessed directly if the row and column that intersect at that cell are known.
A commonly used form of RAM is known as a dynamic RAM (DRAM) device. Dynamic random access memory has memory cells with a paired transistor and capacitor, wherein the capacitor requires continual refreshing. One particular type of DRAM device is a synchronous DRAM (SDRAM) device, in which the device operates synchronously with a clock. To achieve a high-speed operation, a double data rate (DDR) architecture is often used, during which two data transfers are made per clock cycle, one upon the rising edge of the clock and the other on the falling edge.
DRAMs use several on-chip generated voltages for optimized performance. One of these voltages is referred to as the array high voltage VBLH, which supplies power to the bitlines. This voltage is the voltage that is used to write to the cell by a primary sense amplifier. Because each cell along a wordline has to be written again after the read out of the cell signal onto the bitline, a homogenous current flows along the array edge into the sense amplifiers.
Some prior art designs use a feedback regulator with a single output transistor, typically located at the array end, to generate the voltage level VBLH. In this configuration, a large power bus for VBLH along the array edge is used to supply the sense amplifiers with the write current. Ideally, the conductive material used for the VBLH bus has negligible resistance, and thus the voltage along the VBLH bus is constant along the entire length of the VBLH bus.
In reality, the VBLH bus is long enough that, due to the resistivity of the line, a voltage drop exists on the end of the line away from the power source. In other words, the far end of the VBLH bus has a lower VBLH than the near end of the bus. This lower voltage can result in data being lost during a refresh or write cycle. While the bus could be made physically bigger, e.g., to lower the total resistance, the increase in real estate taken by the bus would be undesirable.
Embodiments of the present invention achieve technical advantages by distributing the output transistor along the array edge. Rather than using one large output transistor, several smaller transistors are used to compensate for current drive losses due to the voltage drops along the power bus. The transistors have varying channel widths to ensure a consistent voltage level VBLH. The power bus along the edge of the array comprises the external power supply voltage VDD rather than the voltage VBLH.
In one aspect, the present invention provides a power delivery system for an integrated circuit. This system includes, for example, three power busses (e.g., a VDD bus and two VBLH busses). A first drive transistor is coupled between the first power bus (e.g., VDD) and the second power bus (e.g., one of the VBLH busses) and a second drive transistor is coupled between the first power bus (e.g., VDD) and the third power bus (e.g., the other of the VBLH busses). The second drive transistor has a current path width that is a different width than the current path width of the first transistor. A differential amplifier has a first input coupled to at least one of the second power bus or the third power bus and a second input coupled to a reference voltage node. The output of the differential amplifier is coupled to the control nodes (e.g., gates) of the drive transistors.
In another aspect, the present invention provides a semiconductor memory array, e.g., a DRAM. The device includes an array of memory cells, a plurality of sense amplifiers, a plurality of bitlines, and a plurality of wordlines. Each bitline is coupled to one of the sense amplifiers. A power bus extends adjacent an edge of the array of memory cells. A plurality of drive transistors is disposed at varying locations adjacent the power bus. Each drive transistor is coupled between the power bus and at least one of the sense amplifiers.
Advantages of various aspects of the invention include providing a feedback voltage regulator with a distributed output transistor that allows the power bus along the edge of the array to be smaller, e.g., less wide, thus saving chip area. The VDD bus may have a relatively large voltage drop without negatively affecting the performance of the memory device. The voltage drop on the VBLH line is eliminated, providing a constant output voltage along the array edge. The output transistor comprises a plurality of distributed output transistors having different channel widths to compensate for current drive losses due to voltage drops along the VDD power bus.